We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced CAD/Automation Engineer with experience in digital ASIC design and verification and will develop IP packaging and qualification flow for internal use and external delivery.

The Work:

• Scripting and automation of design database qualification and packaging – languages C-Shell , Perl, Python.
• Integration of foundry libraries, including 5nm/7nm, for IP verification & packaging
• Familiarity with the EDA design flow and tools – Synopsys/ Cadence / Synthesis / Place and Route tools – Design/ FusionCompiler, PrimeTime tool etc.
• Propagation of packaging flow requirements with internal IP teams
• Support and maintenance of qualification tools and scripts (lint, CDC, sim)
• Running of stand-alone IP testbench for qualification
• Initial debug of failures and issues and work w/ IP teams for resolution
• Maintaining package and release timelines for various projects
• Working with cross functional teams (DV/Arch/Design/FW) to ensure quality and completeness of release collaterals